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a
FEATURES High Speed: 50 MHz Unity Gain Bandwidth 350 V/ s Slew Rate 70 ns Settling Time to 0.01% Low Power: 7.5 mA Max Power Supply Current Per Amp Easy to Use: Drives Unlimited Capacitive Loads 50 mA Min Output Current Per Amplifier Specified for +5 V, 5 V and 15 V Operation 2.0 V p-p Output Swing into a 150 Load (VS = +5 V) Good Video Performance Differential Gain & Phase Error of 0.07% & 0.11 Excellent DC Performance: 2.0 mV Max Input Offset Voltage APPLICATIONS Unity Gain ADC/DAC Buffer Cable Drivers 8- and 10-Bit Data Acquisition Systems Video Line Driver Active Filters PRODUCT DESCRIPTION
High-Speed, Low-Power Dual Operational Amplifier AD826
CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP and SO Package
OUT1 -IN1 +IN1 V-
1 2 3 4
8 7 6 5
V+ OUT2 -IN2 +IN2
AD826
The AD826 features high output current drive capability of 50 mA min per amp, and is able to drive unlimited capacitive loads. With a low power supply current of 15 mA max for both amplifiers, the AD826 is a true general purpose operational amplifier. The AD826 is ideal for power sensitive applications such as video cameras and portable instrumentation. The AD826 can operate from a single +5 V supply, while still achieving 25 MHz of bandwidth. Furthermore the AD826 is fully specified from a single +5 V to 15 V power supplies. The AD826 excels as an ADC/DAC buffer or active filter in data acquisition systems and achieves a settling time of 70 ns to 0.01%, with a low input offset voltage of 2 mV max. The AD826 is available in small 8-lead plastic mini-DIP and SO packages.
The AD826 is a dual, high speed voltage feedback op amp. It is ideal for use in applications which require unity gain stability and high output drive capability, such as buffering and cable driving. The 50 MHz bandwidth and 350 V/s slew rate make the AD826 useful in many high speed applications including: video, CATV, copiers, LCDs, image scanners and fax machines.
1k VS 3.3 F
5V
100 90
500ns
0.01 F HP PULSE GENERATOR VIN 1k 50 3 2
CL = 100pF
1/2 AD826
1 VOUT
TEKTRONIX P6201 FET PROBE
TEKTRONIX 7A24 FET PREAMP
10
0.01 F CL 3.3 F -VS
CL = 1000pF
0%
5V
Driving a Large Capacitive Load
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD826-SPECIFICATIONS (@ T = +25 C, unless otherwise noted)
A
Parameter DYNAMIC PERFORMANCE Unity Gain Bandwidth
Conditions
VS 5 V 15 V 0, +5 V 5 V 15 V 0, +5 V 5 V 15 V 5 V 15 V 0, +5 V 5 V 15 V 5 V 15 V 15 V 5 V, 15 V 5 V, 15 V 15 V 5 V 0, +5 V 15 V 5 V 0, +5 V 5 V to 15 V
Min 30 45 25 10 25 10
Typ 35 50 29 20 55 20 15.9 5.6 250 350 200 45 45 70 70 -78 15 1.5 0.07 0.12 0.15 0.11 0.12 0.15 0.5 10 3.3
Max
Unit MHz MHz MHz MHz MHz MHz MHz MHz V/s V/s V/s ns ns ns ns dB nV/Hz pA/Hz % % % Degrees Degrees Degrees mV mV V/C A A A nA nA nA/C V/mV V/mV V/mV V/mV V/mV V/mV k pF V V V V V V dB dB dB REV. B
Bandwidth for 0.1 dB Flatness Full Power Bandwidth1
Gain = +1
Slew Rate
VOUT = 5 V p-p RLOAD = 500 VOUT = 20 V p-p RLOAD = 1 k RLOAD = 1 k Gain = -1 -2.5 V to +2.5 V 0 V-10 V Step, AV = -1 -2.5 V to +2.5 V 0 V-10 V Step, AV = -1 FC = 1 MHz f = 10 kHz f = 10 kHz NTSC Gain = +2 NTSC Gain = +2
200 300 150
Settling Time to 0.1% to 0.01% NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (R1 = 150 ) Differential Phase Error (R1 = 150 ) DC PERFORMANCE Input Offset Voltage
0.1 0.15 0.15 0.15
TMIN to TMAX Offset Drift Input Bias Current TMIN TMAX Input Offset Current TMIN to TMAX Offset Current Drift Open-Loop Gain 0.3 VOUT = 2.5 V RLOAD = 500 TMIN to TMAX RLOAD = 150 VOUT = 10 V RLOAD = 1 k TMIN to TMAX VOUT = 7.5 V RLOAD = 150 (50 mA Output) 5 V 2 1.5 1.5 15 V 3.5 2 15 V 2 4 300 1.5 +4.3 -3.4 +14.3 -13.4 +4.3 +0.9 100 120 100 6 5 4 3 5 V, 15 V 5 V, 15 V
2 3 6.6 10 4.4 300 500
25
INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range
5 V 15 V 0, +5 V
Common-Mode Rejection Ratio
VCM = 2.5 V, TMIN -TMAX VCM = 12 V TMIN to TMAX -2-
5 V 15 V 15 V
+3.8 -2.7 +13 -12 +3.8 +1.2 80 86 80
AD826
Parameter OUTPUT CHARACTERISTICS Output Voltage Swing Conditions RLOAD = 500 RLOAD = 150 RLOAD = 1 k RLOAD = 500 RLOAD = 500 VS 5 V 5 V 15 V 15 V 0, +5 V 15 V 5 V 0, +5 V 15 V Open Loop Min 3.3 3.2 13.3 12.8 +1.5, +3.5 50 50 30 Typ 3.8 3.6 13.7 13.4 Max Unit V V V V V mA mA mA mA
Output Current Short-Circuit Current Output Resistance MATCHING CHARACTERISTICS Dynamic Crosstalk Gain Flatness Match Slew Rate Match DC Input Offset Voltage Match Input Bias Current Match Open-Loop Gain Match Common-Mode Rejection Ratio Match Power Supply Rejection Ratio Match POWER SUPPLY Operating Range Quiescent Current/Amplifier TMIN to TMAX Power Supply Rejection Ratio
NOTES 1 Full power bandwidth = slew rate/2 VPEAK. Specifications subject to change without notice.
90 8
f = 5 MHz G = +1, f = 40 MHz G = -1 TMIN -TMAX TMIN -TMAX VO = 10 V, RLOAD = 1 k, TMIN -TMAX VCM = 12 V, TMIN -TMAX 5 V to 15 V, TMIN -TMAX Dual Supply Single Supply
15 V 15 V 15 V 5 V to 15 V 5 V to 15 V 15 V 15 V 0.15 80 80 2.5 +5
-80 0.2 10 0.5 0.06 0.01 100 100 18 +36 7.5 7.5 7.5 7.5 2 0.8
dB dB V/s mV A mV/V dB dB V V mA mA mA mA dB
TMIN to TMAX VS = 5 V to 15 V, TMIN to TMAX
5 V 5 V 15 V 15 V
6.6 6.8 86
75
ESD SUSCEPTIBILITY
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION - Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 Plastic (N) . . . . . . . . . . . . . . . . . . . . . See Derating Curves Small Outline (R) . . . . . . . . . . . . . . . . See Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 6 V Output Short Circuit Duration . . . . . . . See Derating Curves Storage Temperature Range (N, R) . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 10 seconds) . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability . 2 Specification is for device in free air: 8-lead plastic package, JA = 100C/watt; 8-lead SOIC package, JA = 155C/watt.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD826 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality.
2.0 TJ = +150 C 8-LEAD MINI-DIP PACKAGE 1.5
1.0
0.5 8-LEAD SOIC PACKAGE
ORDERING GUIDE
Model AD826AN AD826AR AD826AR-REEL7 AD826AR-REEL Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic DIP 8-Lead Plastic SOIC 7" Tape & Reel SOIC 13" Tape & Reel SOIC Package Option N-8 SO-8 SO-8 SO-8
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80
90
Maximum Power Dissipation vs. Temperature for Different Package Types
REV. B
-3-
AD826 - Typical Characteristics
QUIESCENT SUPPLY CURRENT PER AMP - mA
20 Volts
7.7
INPUT COMMON-MODE RANGE -
15 +VCM 10 -VCM
7.2
+85 C 6.7 -40 C
+25 C
5
6.2
0
0
5
10 SUPPLY VOLTAGE - Volts
15
20
5.7 0 5 10 SUPPLY VOLTAGE - Volts 15 20
Figure 1. Common-Mode Voltage Range vs. Supply
Figure 4. Quiescent Supply Current per Amp vs. Supply Voltage for Various Temperatures
20
400
Volts
15 RL = 500V 10 RL = 150V 5
SLEW RATE - V/ s
350
OUTPUT VOLTAGE SWING -
300
250
0 0 5 10 SUPPLY VOLTAGE - Volts 15 20
200
0
5
10 SUPPLY VOLTAGE -
15 Volts
20
Figure 2. Output Voltage Swing vs. Supply
Figure 5. Slew Rate vs. Supply Voltage
30
100
OUTPUT VOLTAGE SWING - Volts p-p
25 VS = 20 15V
CLOSED-LOOP OUTPUT IMPEDANCE -
1k 10k
10
15
1
10 VS = 5 5V
0.1
0 10 100 LOAD RESISTANCE -
0.01 1k 10k 100k 1M 10M 100M FREQUENCY - Hz
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 6. Closed-Loop Output Impedance vs. Frequency
-4-
REV. B
AD826
7
100 PHASE 5V OR 15V SUPPLIES
+100
6
80
+80
INPUT BIAS CURRENT - A
5
60
+60
4
40 GAIN 20 5V SUPPLIES
+40
3
+20
2
0 RL = 1k
0
1 -60
-40
-20
0
20
40
60
80
100
120
140
-20 1k 10k 100k 1M 10M FREQUENCY - Hz 100M 1G
TEMPERATURE - C
Figure 7. Input Bias Current vs. Temperature
Figure 10. Open-Loop Gain and Phase Margin vs. Frequency
130
7 15V
SHORT CIRCUIT CURRENT - mA
110 SOURCE CURRENT 90 SINK CURRENT 70
6
OPEN-LOOP GAIN - V/mV
5 5V 4
3
50
2
30 -60
-40
-20
0
20
40
60
80
100
120
140
1 100
1k LOAD RESISTANCE -
10k
TEMPERATURE - C
Figure 8. Short Circuit Current vs. Temperature
Figure 11. Open-Loop Gain vs. Load Resistance
100
100 90
UNITY GAIN BANDWIDTH - MHz
PHASE MARGIN - Degrees
80 PHASE MARGIN
80
80 70 POSITIVE SUPPLY NEGATIVE SUPPLY
PSR - dB
60 50 40 30 20
60
60
GAIN BANDWIDTH 40 40
20 -60
-40
-20
0
20
40
60
80
100
120
20 140
10 100
1k
10k
100k
1M
10M
100M
TEMPERATURE - C
FREQUENCY - Hz
Figure 9. Unity Gain Bandwidth and Phase Margin vs. Temperature
Figure 12. Power Supply Rejection vs. Frequency
REV. B
-5-
PHASE MARGIN - Degrees
OPEN-LOOP GAIN - dB
GAIN
15V SUPPLIES
AD826
140
-40 VIN = 1V p-p GAIN = +2 -50
120
HARMONIC DISTORTION - dB
-60
CMR - dB
100
-70
-80 2ND HARMONIC -90 3RD HARMONIC
80
60 1k 10k 100k FREQUENCY - Hz 1M 10M
-100 100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 13. Common-Mode Rejection vs. Frequency
Figure 16. Harmonic Distortion vs. Frequency
30
50
Hz
OUTPUT VOLTAGE - Volts p-p
20
INPUT VOLTAGE NOISE - nV/
RL = 1k
40
30
20
10
RL = 150
10
0 100k
1M
10M
100M
0 3 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M
FREQUENCY - Hz
Figure 14. Large Signal Frequency Response
Figure 17. Input Voltage Noise Spectral Density
10 0.1% 8
V
380
6
360
OUTPUT SWING FROM 0 TO
2 0 -2 -4 -6 -8 -10 0
1%
0.01%
SLEW RATE - V/ s
80 100 120 140 160
4
340
1%
0.01%
320
0.1%
20
40
60
300 -60
-40
-20
0
20
40
60
80
100
120
140
SETTLING TIME - ns
TEMPERATURE - C
Figure 15. Output Swing and Error vs. Settling Time
Figure 18. Slew Rate vs. Temperature
-6-
REV. B
AD826
5 4 3
VIN 781 VOUT 150
5
2
GAIN - dB
0.1dB VS FLATNESS 15V 55MHz 5V 20MHz 5V 20MHz
GAIN - dB
4 3 2 1
VIN 1k CC
1k
VS
VOUT
CC
0.1dB FLATNESS 16MHz 14MHz 12MHz VS = 15V
15V 3pF 5V 4pF 5V 6pF
1 0 -1 -2 -3 -4 -5 100k VS =
VS =
15V
0 -1 -2 VS = 5V
5V 5V
-3 -4 -5 100k VS = 5V
VS =
1M
10M FREQUENCY - Hz
100M
1M 10M FREQUENCY - HZ
100M
Figure 19. Closed-Loop Gain vs. Frequency
Figure 22. Closed-Loop Gain vs. Frequency, Gain = -1
DIFFERENTIAL GAIN - Percent
0.13
1.0 0.8 0.6 0.4
GAIN - dB
DIFF GAIN
0.10
DIFFERENTIAL PHASE - Degrees
0.13
0.07
0.2 0 -0.2 -0.4 -0.6 -0.8 VS = 5V
VS =
15V
0.12 DIFF PHASE 0.11
VS = +5V
0.10 5 10 SUPPLY VOLTAGE - Volts 15
-1.0 100k
1M 10M FREQUENCY - Hz
100M
Figure 20. Differential Gain and Phase vs. Supply Voltage
Figure 23. Gain Flatness Matching vs. Supply, G = +1
VS
-30
VOUT
0.1 F
-40 -50
CROSSTALK - dB
3 VIN
8
1F 1 7
5 1/2 AD826 6 4 0.1 F
-60 -70 -80 -90 -100 -110 10k 15V RL = 1k 5V RL = 150
1/2 2 AD826
RL
RL 1F -VS
RL = 150
100k 1M FREQUENCY - Hz 10M 100M
FOR
VS = 5V, 1k
FOR
VS = 15V
USE GROUND PLANE PINOUT SHOWN IS FOR MINIDIP PACKAGE
Figure 21. Crosstalk vs. Frequency
Figure 24. Crosstalk Test Circuit
REV. B
-7-
AD826
1k VS 3.3 F
0.01 F
RIN PULSE (LS) VIN 100 OR FUNCTION (SS) 50 GENERATOR
1/2 AD826
VOUT
TEKTRONIX P6201 FET PROBE
TEKTRONIX 7A24 PREAMP
0.01 F RL 3.3 F -VS
Figure 25. Noninverting Amplifier Configuration
5V
100 90
50ns
100 90
200mV
50ns
10 0%
10 0%
5V
200mV
Figure 26. Noninverting Large Signal Pulse Response, RL = 1 k
Figure 28. Noninverting Small Signal Pulse Response, RL = 1 k
5V
100 90
50ns
100 90
5V 200mV
50ns
10 0%
10 0%
5V
200mV
Figure 27. Noninverting Large Signal Pulse Response, RL = 150
Figure 29. Noninverting Small Signal Pulse Response, RL = 150
-8-
REV. B
AD826
1k VS 3.3 F
PULSE (LS) OR FUNCTION (SS) GENERATOR
VIN 50
RIN 1k
0.01 F
1/2 AD826
VOUT 0.01 F RL 3.3 F
TEKTRONIX P6201 FET PROBE
TEKTRONIX 7A24 PREAMP
-VS
Figure 30. Inverting Amplifier Configuration
5V
100 90
50ns
100 90
200mV
50ns
10 0%
10 0%
5V
200mV
Figure 31. Inverting Large Signal Pulse Response, RL = 1 k
Figure 33. Inverting Small Signal Pulse Response, RL = 1 k
5V
100 90
50ns
100 90
200mV
50ns
10 0%
10 0%
5V
200mV
Figure 32. Inverting Large Signal Pulse Response, RL = 150
Figure 34. Inverting Small Signal Pulse Response, RL = 150
REV. B
-9-
AD826
THEORY OF OPERATION INPUT CONSIDERATIONS
The AD826 is a low cost, wide band, high performance dual operational amplifier which can drive heavy capacitive and resistive loads. It also achieves a constant slew rate, bandwidth and settling time over its entire specified temperature range. The AD826 (Figure 35) consists of a degenerated NPN differential pair driving matched PNPs in a folded-cascode gain stage. The output buffer stage employs emitter followers in a class AB amplifier which delivers the necessary current to the load while maintaining low levels of distortion.
+VS
An input protection resistor (RIN in Figure 25) is required in circuits where the input to the AD826 will be subjected to transient or continuous overload voltages exceeding the 6 V maximum differential limit. This resistor provides protection for the input transistors by limiting their maximum base current. For high performance circuits, it is recommended that a "balancing" resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of RIN and RF and thus provides a matched impedance at each input terminal. The offset voltage error will then be reduced by more than an order of magnitude.
APPLYING THE AD826
The AD826 is a breakthrough dual amp that delivers precision and speed at low cost with low power consumption. The AD826 offers excellent static and dynamic matching characteristics, combined with the ability to drive heavy resistive and capacitive loads. As with all high frequency circuits, care should be taken to maintain overall device performance as well as their matching. The following items are presented as general design considerations.
Circuit Board Layout
+IN
CF OUTPUT
-IN
-V S NULL 1 NULL 8
Input and output runs should be laid out so as to physically isolate them from remaining runs. In addition, the feedback resistor of each amplifier should be placed away from the feedback resistor of the other amplifier, since this greatly reduces inter-amp coupling.
Choosing Feedback and Gain Resistors
Figure 35. Simplified Schematic
The capacitor, CF, in the output stage mitigates the effect of capacitive loads. With low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case, CF is bootstrapped and does not contribute to the overall compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the output impedance of the output stage. This reduces the gain, and therefore, CF is incompletely bootstrapped. Effectively, some fraction of CF contributes to the overall compensation capacitance, reducing the unity gain bandwidth. As the load capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier.
In order to prevent the stray capacitance present at each amplifier's summing junction from limiting its performance, the feedback resistors should be 1 k. Since the summing junction capacitance may cause peaking, a small capacitor (1 pF-5 pF) may be paralleled with RF to neutralize this effect. Finally, sockets should be avoided, because of their tendency to increase interlead capacitance.
Power Supply Bypassing
Proper power supply decoupling is critical to preserve the integrity of high frequency signals. In carefully laid out designs, decoupling capacitors should be placed in close proximity to the supply pins, while their lead lengths should be kept to a minimum. These measures greatly reduce undesired inductive effects on the amplifier's response. Though two 0.1 F capacitors will typically be effective in decoupling the supplies, several capacitors of different values can be paralleled to cover a wider frequency range.
-10-
REV. B
AD826
SINGLE SUPPLY OPERATION
R3 and C2 reduce the effect of the power supply changes on the output by low-pass filtering with a corner at
1 . 2R3C2
An exciting feature of the AD826 is its ability to perform well in a single supply configuration (see Figure 37). The AD826 is ideally suited for applications that require low power dissipation and high output current and those which need to drive large capacitive loads, such as high speed buffering and instrumentation. Referring to Figure 36, careful consideration should be given to the proper selection of component values. The choices for this particular circuit are: (R1 + R3) R2 combine with C1 to form a low frequency corner of approximately 30 Hz.
VS
The values for RL and CL were chosen to demonstrate the AD826's exceptional output drive capability. In this configuration, the output is centered around 2.5 V. In order to eliminate the static dc current associated with this level, C3 was inserted in series with RL.
500mV
100
R3 1k
90
3.3 F
C2 0.1 F R1 9k
0.01 F
C1 1F VIN R2 10k
1/2 AD826
RL 150 C3 0.1 F
COUT VOUT CL 200pF
10 0%
500mV
100ns
Figure 36. Single Supply Amplifier Configuration
Figure 37. Single Supply Pulse Response, G = +1, RL = 150 , CL = 200 pF
1k
PARALLEL AMPS PROVIDE 100 mA TO LOAD
By taking advantage of the superior matching characteristics of the AD826, enhanced performance can easily be achieved by employing the circuit in Figure 38. Here, two identical cells are paralleled to obtain even higher load driving capability than that of a single amplifier (100 mA min guaranteed). R1 and R2 are included to limit current flow between amplifier outputs that would arise in the presence of any residual mismatch.
VS
1F
1k
0.1 F
1/2 AD826
VIN
R1 5
VOUT RL
1k
1/2 AD826
0.1 F
R2 5
-VS 1k
1F
Figure 38. Parallel Amp Configuration
REV. B
-11-
AD826
SINGLE-ENDED TO DIFFERENTIAL LINE DRIVER
Outstanding CMRR (> 80 dB @ 5 MHz), high bandwidth, wide supply voltage range, and the ability to drive heavy loads, make the AD826 an ideal choice for many line driving applications. In this application, the AD830 high speed video difference amp serves as the differential line receiver on the end of a back terminated, 50 ft., twisted-pair transmission line (see Figure 40). The overall system is configured in a gain of +1 and has a -3 dB bandwidth of 14 MHz. Figure 39 is the pulse response with a 2 V p-p, 1 MHz signal input.
2V
100 90
200ns
10 0%
2V
Figure 39. Pulse Response
15V 0.01 F 50 FEET TWISTED PAIR Z = 72 15V 0.01 F
IN
0.1 F
2.2 F 36
0.1 F
1.05k BNC 5pF 1.05k 5pF
1/2 AD826
36 VOUT
1.05k 1.05k 36 36
AD830
1/2 AD826
0.01 F -15V -15V 0.1 F 2.2 F
0.01 F
0.1 F
Figure 40. Differential Line Driver
LOW DISTORTION LINE DRIVER
1.1k VS 1F
The AD826 can quickly be turned into a powerful, low distortion line driver (see Figure 41). In this arrangement the AD826 can comfortably drive a 75 back-terminated cable, with a 5 MHz, 2 V p-p input; all of this while achieving the harmonic distortion performance outlined in the following table. Configuration 1. No Load 2. 150 RL Only 3. 150 RL 7.5 RC 2nd Harmonic -78.5 dBm -63.8 dBm -70.4 dBm
1k
0.1 F
1/2 AD826
1k
RC 7.5
1k
In this application one half of the AD826 operates at a gain of 2.1 and supplies the current to the load, while the other provides the overall system gain of 2. This is important for two reasons: the first is to keep the bandwidth of both amplifiers the same, and the second is to preserve the AD826's ability to operate from low supply voltages. RC varies with the load and must be chosen to satisfy the following equation: RC = MRL where M is defined by [(M+ 1) GS = GD] and GD = Driver's Gain, GS = System Gain. -12-
1/2 AD826
1F 75
75
RL 75
0.1 F
Figure 41. Low Distortion Amplifier
REV. B
AD826
HIGH PERFORMANCE ADC BUFFER
1k VS 0.1 F 1k
Figure 42 is a schematic of a 12-bit high speed analog-to-digital converter. The AD826 dual op amp takes a single ended input and drives the AD872 A/D converter differentially, thus reducing 2nd harmonic distortion. Figure 43 is a FFT of a 1 MHz input, sampled at 10 MHz with a THD of -78 dB. The AD826 can be used to amplify low level signals so that the entire range of the converter is used. The ability of the AD826 to perform on a 5 volt supply or even with a single 5 volts combined with its rapid settling time and ability to deliver high current to complicated loads make it a very good flash A/D converter buffer as well as a very useful general purpose building block.
VIN 500mV p-p MAX
50 COAX CABLE 52.5
1/2 AD826
VINA
AD872
12-BIT 10MSPS ADC
1k 5V 100 F 25V COMMON 100 F 25V -5V -VS VS
1/2 AD826
0.1 F
VINB
-VS 1k
Figure 42. A Differential Input Buffer for High Bandwidth ADCs
Figure 43. FFT, Buffered A/D Converter
REV. B
-13-
AD826
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic Mini-DIP (N) Package
C1807a-0-6/00 (rev. B) 00877
45
8 PIN 1 1
5 0.25 (6.35) 4 0.31 (7.87)
0.39 (9.91) MAX 0.0350.01 (0.890.25)
0.30 (7.62) REF
0.1650.01 (4.190.25)
0.125 (3.18) MIN 0.0180.003 (0.460.08) 0.10 (2.54) BSC 0.033 (0.84) NOM
0.180.03 (4.570.76)
0.0110.003 (0.280.08) 15 0
SEATING PLANE
8-Lead SO (R) Package
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
0.0500 (1.27) 0.0160 (0.41)
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
-14-
REV. B
PRINTED IN U.S.A.

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